Flicker Phase-Noise Reduction Using Gate–Drain Phase Shift in Transformer-Based Oscillators

This article presents a wide-band suppression technique of flicker phase noise (PN) by means gate–drain shift in transformer-based complementary oscillator. We identify that after naturally canceling its second-harmonic voltage the operation itself, third-harmonic current entering capacitive path is now main cause asymmetry rising and falling edges, leading to $1/f$ upconversion. A complete notation="LaTeX">$1/f^{3}$ PN analysis for oscillator discussed. By tuning capacitance ratio, specific phase-shift range introduced at gate drain nodes cross-coupled pair mitigate detrimental effects ill-behaved voltage, thus lowering PN. To further reduce area improve thermal region, we introduce new triple-8-shaped transformer. Fabricated 22-nm FDSOI, prototype occupies compact 0.01mm 2 achieves corner 70kHz, −110dBc/Hz 1MHz offset, figure-of-merit (FoM) −182dB 9GHz, 39% range (TR). It results best FoM with normalized TR (FoM TA ) −214dB offset.